1. Field of the Invention
The present invention relates to a multi-layered ceramic capacitor, and in particular, to a multi-layered ceramic capacitor capable of reducing resistance loss by controlling a length of each internal electrode layer to form capacitance.
2. Description of the Related Art
Recently, demand for a micro multi-layered ceramic capacitor has been increased with the miniaturization of electronic devices. A multi-layered ceramic capacitor having small loss characteristics has mainly been used for impedance matching, DC signal interception, and the like, in order to reduce signal loss in devices such as an amplification circuit of a base station of a mobile communications system.
An ideal capacitor has no loss, however, in actuality, a capacitor has both dielectric loss and resistance loss, wherein the magnitude of the loss may be represented by a quality factor (hereinafter, referred to as ‘Q’). In the case that the amount of loss is small, the Q value is large.Q=1/(2πf·C·ESR)
Where f represents a frequency, C represents the capacitance of a capacitor, and ESR represents the equivalent series resistance of a capacitor. Therefore, in order to manufacture the multi-layered ceramic capacitor having a high Q value, the loss of a dielectric material should be small, within a frequency region of several hundred MHz or less, while the resistance loss of the internal electrode should be mainly improved within a frequency region exceeding several hundred MHz.